Not the answer youre looking for Browse other questions tagged digital-logic vhdl shift-register rtl sequential-logic or ask your own question.When the enable signal is high, I want the shift register to shift n times, irrespective of whether enable continues to be high or low.
This means that instead of waiting a clock cycle between each iteration, the entire loop is run within one clock cycle, with only the final result of the loop being shown at the end. ![]() ![]() You can use this to your advantage in order to perform a for-loop type operation, where every iteration of the loop occurs on a clock cycle. Perhaps a wait state for when the process is not shifting, and a shifting state for when it is. Also, at the end of the shift, you can change states back to waiting in order to get ready for enable again. This is useful because generally the asynchronous reset only occurs at startup and is not expected to process any data during this time. By moving the tempreg to the waiting state (outside of the asynchronous reset), we are allowing the module driving parallelin to start up correctly without having to send data during reset. Also, now the waiting state can be entered as necessary, without having to perform an asynchronous reset. If a signal is driven in one process, it shouldnt be driven anywhere else but that process. You can compare the signal to other signals in other places (if statements, and such), but dont give the signal a value anywhere except in one process. And generally, it is defined in the reset portion, and then wherever necessary in the process proper. But only 1 process. If Id been told this, it would have saved me tons of time while I was learning. Parallel Input Serial Output Shift Register Vhdl Code Driver Error WhatAll too often am I met with the multiple driver error What exactly is sin doing here This shift register seems to latch in the parallel data and then shift out serially. It is otherwise unused, OP must explain what it was originally intended for. I agree that a SISO register should be otherwise strictly serial. Parallel Input Serial Output Shift Register Vhdl Code Free Time AndMy coding practices have changed since then and Im sure there are multiple things anyone could fine wrong with this, since I wrote it in my free time and not as a rigorous academic exercise. You are welcome to write an answer if you think mine is inadequate. I would say the loop is expanded at elaboration time (compilation), not that it executes in zero time, after all at runtime there will still be propagation delay through the elements generated by the for construct. At the end of the day HDL is just a text-based way of expressing the content of logic schematics. If you consider the generate statement then your description is true, but if you consider the loop statement inside a process, this is sequential code. ![]() The reputation requirement helps protect this question from spam and non-answer activity.
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